Integrated circuits are usually produced by forming a plurality of integrated circuits on a semiconductor wafer substrate by repeatedly exposing the wafer to a reticle mask utilizing a stepper, thereby forming a plurality of exposed areas arranged on the wafer surface. The image of the mask pattern is printed on a resist layer applied on the wafer surface and developed to form a resist pattern used as a mask for, for instance, etching a layer formed on the wafer surface. The integrated circuits are formed by repeating these processes. The individual integrated circuits are separated by saw lines used for a successive separation step.
In addition to the integrated circuits, test devices for measuring electric characteristics are also formed on the wafer substrate. The test devices are usually known as process control modules (PCM), may include active or passive electric devices, such as transistors or resistive tracks, and are usually located within the saw lines.
Published U.S. application for patent No. 2003/0017631 A1 discloses a reticle including a device pattern region, in which a plurality of mask patterns of semiconductor device chips is formed, and including a test element group (TEG) pattern region formed on one side of the device pattern region. The TEG pattern region is provided for arranging patterns of TEGs and alignment marks for the exposing apparatus. The lateral dimension of the TEG pattern region is the same as that of the device pattern region. The width, i.e. the vertical dimension, of the TEG pattern region corresponds to two rows of the semiconductor device chip patterns.